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KA3842AC
SMPS Controller
Features
* * * * * * * Low Start Current 0.2mA (Typ) Operating Range up to 500kHz Cycle by Cycle Current Limiting Under Voltage Lock Out With Hysteresis Short Shutdown Delay Time: Typ.100ns High Current Totem-Pole Output Output Swing Limiting: 22V
Description
The KA3842AC are fixed PWM controller for Off Line and DC to DC converter applications. The internal circuits include UVLO, low start up current circuit, temperature compensated reference, high gain error amplifier, current sensing comparator, and high current totem pole output for driving a POWER MOSFET. Also KA3842AC provides low start up current below 0.3mA and short shutdown delay time typ. 100ns. The KA3842AC has UVLO threshold of 16V(on) and 10V(off). The KA3842AC can operate within 100% duty cycle.
8-DIP
1
Internal Block Diagram
7 VCC 29V
VREF 8
Internal Bias 1/2VREF
5V VREF
SET/ RESET UVLO
5 GND
Good LOGIC 7 Error Amp + C.S PWM Comp. LATCH 1/3 1V S R 22V 6 OUTPUT
PWR VC
VFB 2
COMP 1
5 PWR
C.S 3 RT/CT 4
T
GND
OSCILLATOR
Rev. 1.0.0
(c)2005 Fairchild Semiconductor Corporation
KA3842AC
Absolute Maximum Ratings
Parameter Supply Voltage Output Current Analog Inputs (Pin2, 3) Error Amp. Output Sink Current Power Dissipation Thermal Resistance, Junction-to-Air (Note4) Symbol VCC IO VI(ANA) ISINK(EA) PD Rja Value 30 1 -0.3 to 6.3 10 1 95 Unit V A V mA W C/W
Electrical Characteristics
(VCC = 15V, RT = 10k, CT = 3.3nF, TA = 0C to +70C ,Unless otherwise specified) Parameter REFERENCE SECTION Output Voltage Line Regulation Load Regulation Output Short Circuit OSILLATOR SECTION Initial Accuracy Voltage Stability Amplitude Discharge Current CURRENT SENSE SECTION Gain Maximum Input Signal PSRR Input Bias Current Delay to Output VREF VREF VREF ISC FOSC STV VOSC IDISCHG GV VI(MAX) PSRR IBIAS TD TJ = 25C, IO = 1mA VCC = 12V to 25V IO = 1mA to 20mA Ta = 25C TJ = 25C VCC = 12V to 25V VPIN4, Peak to Peak TJ = 25C, Pin4 = 2V (Note2, 3) VPIN1 = 5V(Note2) VCC = 12V to 25V (Note1, 2) VPIN3 = 0 V to 2V (Note1) 4.9 47 7.8 2.85 0.9 5.0 6 6 -100 52 0.2 1.7 8.3 3 1.0 70 -2 100 5.1 20 25 -180 57 1 8.8 3.15 1.1 -10 200 V mV mV mA kHz % V mA V/V V dB uA ns Symbol Conditions Min. Typ. Max. Unit
2
KA3842AC
Electrical Characteristics (Continued)
(VCC = 15V, RT = 10k, CT = 3.3nF, TA = 0C to +70C, Unless otherwise specified) Parameter ERROR AMPLIFIER SECTION Input Voltage Input Bias Current Open Loop Gain Unity Gain Bandwidth PSRR Output Sink Current Output Source Current Output High Voltage Output Low Voltage OUTPUT SECTION Output Low Level Output High Level Rise Time Fall Time Output Voltage Swing Limit Start Threshold Min. Operating Voltage ( After turn on ) PWM SECTION Maximum Duty Cycle Minimum Duty Cycle TOTAL STANDBY CURRENT Start-Up Current Operating Supply Current VCC Zener Voltage IST ICC VZ ICC = 25mA VPIN2 = VPIN3 = 0V 0.2 11 29 0.4 17 mA mA V DMAX DMIN KA3842AC 94 96 100 0 % % VOL VOH tR tF VOLIM VTH VTL ISINK = 20mA ISINK = 200mA ISOURCE = 20mA ISOURCE = 200mA TJ = 25C, C1 = 1nF (Note1) TJ = 25C, C1 = 1nF (Note1) VCC = 27V, C1 = 1nF KA3842AC KA3842AC 13 12 15 9 0.1 1.5 13.5 13.5 40 40 22 16 10 0.4 2.2 100 100 17 11 V V V V ns ns V V V VI IBIAS GVO GBW PSRR ISINK ISOURCE VOH VOL TJ= 25C (Note1) VCC = 12V to 25V (Note1) VPIN2 = 2.7V VPIN1 = 1.1V VPIN2 = 2.3V VPIN1 = 5.0V VPIN2 = 2.3V R1 = 15k to GND VPIN2 = 2.7V R1 = 15k to Pin8 TPIN1 = 2.5V VO = 2V to 4V (Note1) 2.42 65 0.7 60 2 -0.5 5 2.50 -0.3 90 1 70 6 -0.8 6 0.8 2.58 -2 1.1 V uA dB MHz dB mA mA V V Symbol Conditions Min. Typ. Max. Unit
UNDER VOLTAGE LOCKOUT SECTION
* Adjust VCC above the start threshold before setting at 15V Notes : 1. These parameters, although guaranteed, are not 100% tested in production. 2. Parameter measured at trip point of latch with V2 = 0V. 3. Gain defined as: GV = VPIN1VPIN3(VPIN3 = 0 to 0.8V) 4. Junction-to-air thermal resistance test enviroments. -. PCB information ; Board thickness : 1.6mm , Board dimension : 76.2 X 114.3mm2 , Ref. : EIA / JSED51-3 and EIA / JSED51-7 -. Board structure; Using the single layer PCB.
3
KA3842AC
Mechanical Dimensions
Package
8-DIP
0.018 0.004 1.524 0.10 0.060 0.004 0.46 0.10 6.40 0.20 0.252 0.008 ( #1 #8 9.20 0.20 0.362 0.008 9.60 MAX 0.378 #4 #5 2.54 0.100 5.08 MAX 0.200 7.62 0.300 3.40 0.20 0.134 0.008 3.30 0.30 0.130 0.012 0.33 MIN 0.013
0.25 -0.05
0~15
+0.10
0.010 -0.002
+0.004
4
0.79 ) 0.031
KA3842AC
Ordering Information
Product Number KA3842AC Package 8-DIP Operating Temperature 0 ~ +70C
5
KA3842AC
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 3/2/05 0.0m 001 Stock#DSxxxxxxxx " 2005 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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